1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a static semiconductor memory device capable of reducing a standby current.
2. Description of the Background Art
Random access memories, a memory device into which data can be written, stored and read in a nonsequential manner, are classified into a dynamic random access memory (DRAM) in which cells require a refresh operation for holding a stored data and a static random access memory (SRAM) with no need of the refresh operation, in a broad sense.
Since SRAM has a complex structure and a high cost per each unit capacity as compared with DRAM, but requires no refresh operation, SRAM contains a feature that data can be read and written at high speed. For such a reason, SRAM is used in a cash memory requiring a comparably fast operation in a high speed CPU (a central processing unit) or the like. Especially, in recent years, SRAM has found its wide application in a battery-driven portable terminal equipment and others, using a feature of its comparably low power consumption.
FIG. 14 is a circuit diagram representing an example configuration of a memory cell of SRAM. In FIG. 14, shown is a so-called CMOS memory cell constructed of six MOS transistors.
Referring to FIG. 14, MOS transistors QP1, QP2, QN1 and QN2 constitute two CMOS inverters for holding signal levels at storage nodes Nm and /Nm. Writing and reading datas onto or from the storage node Nm and /Nm are performed in such a manner that access transistors QN3 and QN4 responsive to activation (H level) of a word line WL are turned on and thereby, the storage node Nm and /Nm are coupled to bit lines BL and /BL, respectively.
When a word line WL is inactivated (L level) and access transistors QN3 and QN4 are turned off, MOS transistors of different conductivity types in the respective CMOS inverters are turned on according to data levels held in the storage nodes Nm and /Nm. Thereby, the storage nodes Nm and JNm couple selectively with a power supply potential Vcc corresponding to H level of a data and the ground potential Vss corresponding to L level of a data, respectively, in this order or in the reverse way thereof according to a level of a data held in a memory cell. By doing so, a data can be held in a memory cell with no periodical refresh operation following turning on of a word line WL.
FIG. 15 is a circuit diagram representing another example configuration of a SRAM.
In FIG. 15, a storage nodes Nm and /Nm are coupled with the power supply potential Vcc through high resistance loads R1 and R2, respectively. Access transistors N type MOS transistors QN1 and QN2 are electrically coupled between the storage node Nm and the ground potential Vss, and between the storage node /Nm and the ground potential Vss, respectively.
Writing and reading of datas onto and from the storage nodes Nm and /Nm are, similar to the case of FIG. 14, are performed by coupling the storage nodes Nm and /Nm with bit lines BL and /BL, respectively, through turning on of the access transistors QN3 and QN4 responsive to activation (H level) of a word line WL.
In a case where the word line WL is inactivated (L level) and the access transistors QN3 and QN4 are turned off, one of the transistors QN1 and QN2 is turned on according to data levels held in the storage nodes Nm and /Nm, and thereby, the storage nodes Nm and /Nm are selectively set to the power supply potential Vcc and the ground potential Vss, respectively, in this order or in the reverse way, according to a level of a data stored in a memory cell. By doing so, potential levels of the storage nodes Nm and /Nm are held even in the standby state.
As shown in FIGS. 14 and 15, the power supply potential Vcc and the ground potential Vss are all the time supplied to a SRAM memory cell. In order to efficiently supply the power supply potential Vcc and the ground potential Vss to memory cells arranged in a matrix, lines supplying the potentials are generally placed along a row or column direction.
FIGS. 16 and 17 are block diagrams representing an example and another example, respectively, of placement of power supply lines in a SRAM memory array.
Referring to FIG. 16, memory cells MC are arranged in a matrix of (n+1) rows and (m+1) columns, where n and m are a natural number. Word lines are placed along the respective rows corresponding thereto. In an entire memory cell array MCA, word lines WL0 to WLn are placed along respective (n+1) memory cell rows corresponding thereto.
Bit line pairs are likewise placed along respective memory cell columns corresponding thereto. A bit line pair is constituted of two data lines carrying complementary datas thereon. For example, a bit line pair BLP0 is constituted of bit lines BL0 and /BL0. The bit line /BL0 carries a data of an opposite polarity from that of a data transmitted on the bit lime BL0. In the entire memory cell array MCM, bit line pairs BLP0 to,BLPm are placed along respective (m+1) memory cell columns corresponding thereto.
In FIG. 16, shown is a configuration in which power supply lines are placed along respective memory cell rows corresponding thereto. That is, the power supply lines 100-0 to 100-n are placed along the respective memory cell rows corresponding thereto. The power supply lines 100-0 to 100-n are coupled with a main power supply line 70 supplying the power potential Vcc.
In a configuration of FIG. 16, power supply lines can be placed corresponding to respective sets of a plurality of memory cell rows as well in this case, for example, one power supply line is allocated to each pair of two memory cell rows or each set of 3 memory cell rows.
In FIG. 17, shown is a configuration in which power supply lines are placed along a memory cell column direction. Referring to FIG. 17, power potential supply lines 100-0 to 100-m for transmitting the power supply potential Vcc to the respective memory cells MC are provided along the respective memory cell columns corresponding thereto. The power potential supply lines 100-0 to 100-m are coupled with the main power supply line 70.
In a configuration of FIG. 17, power supply lines are placed corresponding to respective sets of a plurality of memory cell columns as well.
As shown in FIGS. 16 and 17, when the power supply lines are provided along a row or column direction of the memory cells, the power supply potential Vcc can be efficiently supplied to each of the memory cells in a memory cell array. Though detailed description is omitted, lines supplying the ground potential Vss to each of the memory cells MC through a main ground line 80 are arranged, similar to the power potential supply lines.
However, since, in a SRAM memory cell, the power supply potential Vcc and the ground potential Vss are supplied all the time, a current flows in the memory cell all the time when a short-circuit current path arises between the power supply potential Vcc and the ground potential Vss due to a defect.
Such a defective memory cell can be replaced for repairing with a spare memory cell provided in advance from the viewpoint of data storage. Even when a defective memory cell has been replaced for repairing, however, a short circuit current produced between the power supply potential Vcc and the ground potential Vss in the defective memory cell continues to flow.
Therefore, when a SRAM memory is mounted on an information terminal equipment or the like and a small operating current is required especially in a standby state, a defective memory cell in which a short circuit current path is present cannot be saved, which causes an obstacle against ensuring product yield of SRAM.
It is accordingly an object of the present invention to provide a static semiconductor memory device capable of suppressing a current consumed in a standby state even when a defective memory cell containing a short-circuit current path between a power supply potential and a ground potential arises.
The present invention will be summarized: the present invention is directed to a semiconductor memory device having an operating state to perform reading and writing data and a standby state to hold a data, includes: a plurality of memory cells; a main power supply line; a first power supply line; a second power supply line; and a current limiter. The plurality of memory cells are arranged in a matrix and each memory cell holds a data, receiving a first potential and a second potential corresponding to a high level and a low level, respectively, of the data. The main power supply line supplies the first potential. The first power supply line is placed in each of sections among the plurality of memory cells to supply the first potential to memory cells in the corresponding section. The second power supply line supplies the second potential to the plurality of memory cells. The current limiter is provided between the main power supply line and the first power supply line in order to limit a current amount passing through the first power supply line below a prescribed value in the standby state.
Accordingly, a main advantage of the present invention is in that a current consumed in the standby state is suppressed to a prescribed value or lower such that a standard value of power consumption in a semiconductor device can be met even when a defective memory cell in which a short-circuit path is caused between the first and second power supply lines arises and replacement saving becomes necessary.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.